(1) Field of the Invention
The present invention relates to a structure of a charge transfer device, and more particularly to the structure of the load resistance of a source follower used in its output circuit.
(2) Description of the Related Art
A conventional charge transfer device of the kind to which the present invention relates is first explained with reference to FIGS. 1A and 1B, FIGS. 2A and 2B, and FIGS. 3A and 3B. FIG. 1A shows an outline of the condition of an output section of the conventional charge transfer device. In FIG. 1A, the numeral 1 indicates a p-type semiconductor substrate, 2a indicates an n-type semiconductor region consisting of a charge transfer region and a floating diffusion layer region constituted inside the p-type semiconductor substrate 1, 4 indicates an n.sup.+ -type semiconductor region which is also constituted inside the p-type semiconductor substrate 1 and which gives a reset voltage to the floating diffusion layer, and 5 indicates a p.sup.+ -type semiconductor region which is constituted inside a surface region of the p-type semiconductor substrate 1 and which becomes a device isolating region. Further, on the n-type semiconductor region 2a, with an insulating film interposed, there are a plurality of conductive electrodes 7a, 7b and 7c constituting charge transfer electrodes, a conductive electrode 7d constituting an output gate electrode, and a conductive electrode 7e constituting a reset gate electrode. The n-type semiconductor region 2a and each of the charge transfer electrodes 7a, 7b and 7c constitute a charge transfer register.
Clock pulses .PHI.1, .PHI.2, .PHI.3, each differing in phase by 120.degree. as shown in FIG. 1B, are respectively applied to interconnecting lines respectively connected to the charge transfer electrodes. As a result of this, for example, the signal charge below the conductive electrode 7a constituting a charge transfer electrode, is sequentially transferred to below the conductive electrodes 7b and 7c constituting charge transfer electrodes, and finally, after passing through the semiconductor region below the conductive electrode 7d constituting the output gate electrode, is transferred to the floating diffusion layer region of the n-type semiconductor region 2a. The potential change in the floating diffusion layer region due to the transfer of the signal charge is inputted to the gate of a MOSFET 8, and then, after an impedance conversion being performed by a source follower circuit constituted by this transistor and a load resistance 9 connected to the source of this transistor, is derived as a voltage output signal from an output terminal V.sub.OUT. (Reference publication: W. F. Kosonocky and J. E. Carnes: Two-Phase Charge-Coupled Devices with Overlapping Polysilicon and Aluminium Gates, RCA Review Vol. 34, pp. 164-202).
FIG. 2A is a circuit diagram of the source follower, and FIG. 2B is an equivalent circuit diagram thereof. From the equivalent circuit diagram of FIG. 2B, the voltage gain V.sub.2 /V.sub.1 of the source follower is expressed as follows: EQU V.sub.2 /V.sub.1 =g.sub.m r.sub.ds R.sub.s / (R.sub.s +r.sub.ds +g.sub.m r.sub.ds R.sub.s)
but actually, r.sub.ds &gt;&gt;R.sub.s and hence, EQU V.sub.2 /V.sub.1 =g.sub.m R.sub.s / (1+g.sub.m R.sub.s).
On the other hand, the output impedance, Z.sub.o is, EQU Z.sub.o =R.sub.s r.sub.ds / (R.sub.s +r.sub.ds +g.sub.m r.sub.ds R.sub.s)
can be obtained.
Here, if we let, R.sub.s =200 .OMEGA., g.sub.m =20.times.10.sup.-3 .OMEGA..sup.-1, r.sub.ds =10.sup.4 .OMEGA., then,
the voltage gain, V.sub.2 /V.sub.1 =0.8, and
the output impedance, Z.sub.o =40 .OMEGA.,
hence, the source follower in which, although the voltage gain is less than 1 and the input impedance is large, the output impedance is smaller than the source load resistance, is suitable for impedance conversion and is widely used as the output circuit for charge transfer devices.
FIGS. 3A and 3B are the cross-sectional diagrams of MOSFETs that are presently widely used as the source load resistance of the source followers shown in FIG. 1A. FIG. 3A shows a surface type MOSFET, and in the same diagram, the numeral 1 indicates a p-type semiconductor substrate, 4 indicates an n.sup.+ -type semiconductor region that constitutes the source/drain region, 5 indicates a p.sup.+ -type semiconductor region that constitutes the device isolating region, 6 indicates a gate insulating film, and 7h indicates a conductive electrode that constitutes a gate electrode.
Further, FIG. 3B shows a buried type MOSFET, and in the same figure, the numeral 1 indicates a p-type semiconductor substrate, 2a indicates an n-type semiconductor region, 4 indicates an n.sup.+ -type semiconductor region that constitutes the source/drain region, 5 indicates a p.sup.+ -type semiconductor region that constitutes the device isolating region, 6 indicates a gate insulator film, and 7i indicates a conductive electrode that constitutes a gate electrode.
Each of the n.sup.+ -type semiconductor regions of the drain side of the MOSFETs shown in FIG. 3A and 3B is connected to a node "A" of the source follower shown in FIG. 1A.
In both the cases, the MOSFETs are designed to be used in the saturation state with the stability of voltage gain being taken into considerations. In the buried type MOSFET shown in FIG. 3B, electrons pass through a bulk region separated from the silicon/oxide film interface, so that the contact with the interface level existing at the silicon/oxide film interface is reduced in comparison to the surface type MOSFET of FIG. 3A, enabling low noise capability.
However, with the advance of manufacturing technology of semiconductor integrated circuits and the progress in miniaturization/compactness of charge transfer devices, the accompanying reduction in the number of electrons constituting the signal makes it difficult to obtain an output signal with a high signal/noise (S/N) ratio. The degradation of the S/N ratio can be further enhanced by charge transfer devices using output circuits of the conventional type technology as described above. This is because the channel of the MOSFET constituting the source load resistance in the conventional output circuits is not completely separated from the interface level at the silicon/oxide film interface, which is obvious in the case of the surface type as shown in FIG. 3A, and also in the case of the buried type as shown in FIG. 3B.
Thus, in solid state imaging devices constituted using such conventional charge transfer devices, the degradation of picture quality caused by S/N degradation is a defect.